Adam T. Arnesen
Staff Software EngineerNational Instruments LabVIEW R&D 11500 N. Mopac Expwy. Austin, TX, 78759-3504 Office: (512) 683-5118 Email: firstname.lastname@example.org
Adam Arnesen received his M.S. in Electrical and Computer Engineering in 2011 from Brigham Young University. He also received his B.S. in Electrical Engineering in 2009 also from Brigham Young University. While working on his masters degree, Adam worked at the Configurable Computing Lab at BYU as part of the NSF Center for High-Performance Reconfigurable Computing (CHREC).
Adam’s professional interests include Intellectual Property (IP) core reuse in in reconfigurable computing (RC) platforms including FPGA, formal representation of interface behavior for RC cores, and interface synthesis for FPGA. Adam currently works on the LabVIEW FPGA compiler team at National Instruments.
- A. Arnesen, “Increasing Design Productivity for FPGAs Through Intellectual Property Reuse and Meta-Data Encapsulation,” M.S. Thesis, Dept of Electrical and Computer Engineering, Brigham Young University, Provo, Utah, 2011
- N. Rollins, A. Arnesen, and M. Wirthlin, “An XML schema for Representing Reuable IP Cores for Reconfigurable Computing,” in Proceedings of the National Aerospace and Electronics Conference (NAECON 2008), July 2008. (Available Here)
- A. Arnesen, N. Rollins, and M. Wirthlin, “A Multi-Layered XML Schema and Design Tool for Reusing and Integrating FPGA IP,” Proc. of 19th International Conference on Field Programmable Logic and Applications (FPL 2009), August 2009. (Available Here)
- A. Arnesen, K. Ellsworth, D. Gibelyou, T. Haroldsen, J. Javican, M. Padilla, B. Nelson, M. Rice, M. Wirthlin, “Increasing Design Productivity Through Core Reuse, Meta-Data Encapsulation, and Synthesis,” Proc. of 20th International Conference on Field-Programmable Logic and Applications (FPL 2010), September 2010. (Available Here)
- A. Arnesen, “Meta-data and Interface Synthesis Techniques for Improving Design Productivity in Reconfigurable Computing,” in proceedings of the Rocky Mountain NASA Space Grant Consortium, May 2010 (Available Here)
- A. Arnesen, “Meta-Data-Enabled Reuse of Dataflow IntellectualProperty for FPGAs,” in proceedings of the Rocky Mountain NASA Space Grant Consortium, May 2011 (Available Here)
- CHREC June Meeting 2008, Provo UT
- CHREC December Meeting 2009, Orlando FL
Graduate School Projects Wiki
- Array Multiplier and Pipelining Experiments
- Ambric Implementation of Image Skeletonization Algorithm
- CUDA Implementation of CT Backprojection Reconstruction
- Altera Tech-mapper for JHDL
A full summary of my work is available at my online resume.
A PDF of my resume is available here.